Apple Xserve G5 Spezifikationen

Xserve G5 Developer Note2005-01-04

10Organization of This Document2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.INTRODUCTIONIntroduction to Xserve G5 Developer Note

The Xserve G5 is the Macintosh server platform using the PowerPC G5 microprocessor. It has arack-mount enclosure and includes server-oriented features

Additional FeaturesA high-speed bus architecture between the memory controller and deviceI/O. For more information, see “HyperTransport Technology” (p

A high-speed bus architecture between the memory controller and deviceI/O. For more information, see “HyperTransport Technology” (page 25)Hyper Transp

Note: Depending on the configuration of your Xserve G5, the appearance may differ slightly fromthe illustrations.Figure 1-1 Xserve G5 slot load front

Figure 1-2 Xserve G5 slot load and cluster node back panelUSB ports (2)Gigabit Ethernet port(s)System identifier button/lightPower socketFireWire 800

The bottom row of system activity lights on the Xserve G5 (shown in Figure 1-1 (page 14) and Figure1-3 (page 15) indicates the state of the computer w

An editable UPS shutdown script that will run when the machine powers down because of UPSis available in the /user/libexec/upsshutdown directory. Aut

man diskutil Remote volume configuration: The system software can remotely configure newly mountedvolumes. USB and FireWire alerts: Xserve G5’s keys

For both Xserve G5 configurations, the value of the model property is RackMac3,1.Velocity Engine AccelerationThe Velocity Engine (an implementation of

Apple Inc.© 2002, 2005 Apple Computer, Inc.All rights reserved.No part of this publication may bereproduced, stored in a retrieval system, ortransmitt

20System Software2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.CHAPTER 1Overview of the Xserve G5

This chapter describes the architecture of the Xserve G5. It includes information about the majorcomponents on the logic boards: the microprocessor, t

Figure 2-1 Simplified block diagramSerial port1.5 GbpsSerial ATA bus10/100/1000 Ethernet port10/100/1000 Ethernet port400 MHzECC DDRmemory busProcesso

Internal PCI bus: 33 MHz, 32-bit bus supports the K2 I/O controller, the boot ROM, and the USBcontrollers Serial ATA (SATA) bus: supports 1.5 Gbps

Note: The Xserve G5 does not use jumpers to control the clock speeds of the processor and cache.Dual ProcessorsThe dual-processor configurations of th

HyperTransport TechnologyThe DDR HyperTransport is an advanced chip-to-chip communications technology that provides ahigh-speed, high-performance, poi

The U3H IC used in the Xserve G5 supports the PCI write combining feature. This feature allowssequential write transactions involving the Memory Write

Internal PCI BusAn internal 33-MHz, 64-bit PCI bus connects the K2 I/O controller to the boot ROM and the USBcontroller. The internal PCI bus offers n

FireWire ControllersThe K2 IC includes a FireWire controller that supports both IEEE 1394b (FireWire 800) with a maximumdata rate of 800 Mbps (100 MBp

Optional Graphics CardThe Xserve G5 has a build-to-order option of an ATI RV100 64 MB RAM VGA/PCI graphics cardwith a VGA connector. The ATI RV100 run

ContentsIntroductionIntroduction to Xserve G5 Developer Note 9Organization of This Document 9Chapter 1Overview of the Xserve G5 11Hardware Features 11

30Optional Graphics Card2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.CHAPTER 2Architecture

This chapter describes the Xserve G5’s built-in I/O devices and the ports for connecting external I/Odevices. Each of the following sections describes

Table 3-1 Signals on the USB connectorDescriptionSignal namePin+5 VDCVCC1Data –D–2Data +D+3GroundGND4The Xserve G5 provides power for the USB ports at

FireWire 800 ConnectorThe FireWire 800 port on the Xserve G5 is based on IEEE 1394b and enables a 800 Mbps transfer rate.FireWire 800 uses a 9-pin con

The 9-pin FireWire port is capable of operating at 100, 200, 400, and 800 Mbps, depending on thedevice it is connected to. Using a cable with a 9-pin

The power pin provides up to 15 W total power for all three FireWire connectors. The voltage on thepower pin can be from 18 to 25 V.Pin 2 of the FireW

Signal definitionSignal namePinReceive (negative lead)RXN6Not used–7Not used–8Table 3-5 Signals for 1000Base-T operationSignal definitionSignal namePi

Figure 3-4 Serial port connector1 2 3 4 567 8 9Table 3-6 Serial port signalsSignal descriptionSignal namePinReceived line signal detectorRLSD1Received

Writing speedReading speedMedia type24x (ZCLV)24x (CAV max)CD-R16x (ZCLV, for Ultra speed media)24x (ZCAV max)CD-RW–24x (CAV max)CD or CD-ROMSuperDriv

Note: Pin eleven supports the drive activity light. For full functionality of the drive activity light andsystem monitoring, use Apple drives. Other d

Power Controller 28Dual System Monitor ICs 28System Activity Lights 28Device Identification 28Optional Graphics Card 29Chapter 3Input and Output Devic

DescriptionSignal namePinGreen video signal returnGREEN_RTN7Blue video signal returnBLUE_RTN8No connectn.c.9GroundGND10No connectn.c.11I2C dataSDA12Ho

This chapter describes the RAM expansion slots and the PCI expansion slots of the Xserve G5.RAM ExpansionThe main logic board of the Xserve G5 has fou

The Serial Presence Detect (SPD) EEPROM specified in the JEDEC standard is required and must beset to properly define the DIMM configuration. The EEPR

Table 4-2 Address multiplexing modes for ECC DDR SDRAM devicesSize of column addressSize of row addressDevice configurationDevice size10124 M x 8 x 41

44PCI and PCI-X Expansion Slots2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.CHAPTER 4Expansion

For more information about the technologies mentioned in this developer note, you may wish toconsult some of the references listed in the following se

Mac OS X and Mac OS ServerFor access to Apple’s developer documentation for Mac OS X, see the website athttp://developer.apple.com/documentation/MacOS

http://developer.apple.com/technotes/tn/tn1062.htmlTN 1044: Open Firmware, Part III, athttp://developer.apple.com/technotes/tn/tn1044.htmlOther techni

Serial ATAFor information on Serial ATA specifications and design guides, go to the World Wide Web athttp://www.serialata.orgUSB InterfaceFor more inf

Serial Interface StandardsThe Telecommunications Industry Association (TIA) is the trade organization that publishes thestandards for the RS-232 seria

Serial Interface Standards 49Appendix BConventions and Abbreviations 51Typographical Conventions 51Abbreviations 51Index 5552005-01-04 | © 2002, 2005

50Serial Interface Standards2005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.APPENDIX ASupplemental Reference Documents

This developer note uses the following typographical conventions and abbreviations.Typographical ConventionsNote: A note like this contains informatio

secondssec.kilogramskgvoltsVkilohertzkHzwattsWkilohmskpoundslb.Other abbreviations used in developer notes include these:Apple drive moduleADMadvanced

Institute of Electrical and Electronics EngineersIEEEthe official specification for Open FirmwareIEEE 1274the official specification for FireWire 400I

read-only memoryROMstandard serial interfaceRS-232standard serial interfaceRS-422Serial Bus ProtocolSBPSerial Presence DetectSPDSmall Computer System

Aabbreviations 51–54AltiVec 19Apple PI elastic buses 24Bblock diagram 21block diagramsmain logic board 22boot ROM 27bootFireWire 35headless 17, 29boot

GG5, See PowerPC G5 microprocessorgraphics support 25HHyperTransport 25II/O portsEthernet 35FireWire 32video monitor 39interrupts 26KK2 I/O controller

video monitor ports 39VGA 39Wwrite combining 26, 27572005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.INDEX

62005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.CONTENTS

Figures and TablesChapter 1Overview of the Xserve G5 11Figure 1-1 Xserve G5 slot load front panel 14Figure 1-2 Xserve G5 slot load and cluster node ba

82005-01-04 | © 2002, 2005 Apple Computer, Inc. All Rights Reserved.FIGURES AND TABLES

This developer note describes Apple Computer’s Xserve G5. The note provides information aboutthe internal design of the computer, its input-output and