SECTION I11
HOW TO EXPAND THE APPLE SYSTEM
The Apple system can be expanded to in-
clude more memory and
I0 devices, via a 44-pin
edge connector. The system is fully expandable
to
65K, with the entire data and address busses,
clocks, control signals
(
i.
e. IRQ, NMI, DMA,
RDY, etc.), and power sources available at the
connector. All address lines are TTL buffered,
and data lines can drive ten equivalent capacitive
loads (one TTL load and 130pf) without external
buffers. All clock signals are TTL. The Apple
system runs at approximately 1 MHz
(
see spec
sheet) and is fully compatible with 6800/6500 style
timing.
Three power sources are available at the
edge connector: f5 volts regulated, and raw DC
(approximately
+/-
14V) for the +12'V, -12V, and
-5V supplies.
If
+12V, -12V, or -5V supplies are
required, EXTERNAL REGULATORS MUST BE
USED. An excess of 1.5 amps from the "on-
boardu regulated
f5V supply is available for ex-
pansion (assuming suitable transformer ratings
are employed). Exercise great care in the handling
of the raw DC, as no short-circuit protection is
provided.
REFRESH:
Four out of every 65 clock cycles is dedi-
cated to memory refresh. At the start of a re-
-
fresh cycle (150 ns after leading edge of 01), RF
goes low, and remains low for one clock cycle.
$42 is inhibited during a refresh cycle, and the
processor is held in 01 (it's inactive state). Dy-
namic memories, which must clock during refresh
cycles, should derive their clock from 00, which
is equivalent to 02, except that it continues during
a refresh cycle. Devices, such as PIA1s, will not
be affected by a refresh cycle,
since they react to
02 only. Refer to Apple "TechNotesl' for a variety
of inte riacing examples
.
DMA:
The Apple system has full DMA capabli
For DMA, the DMA control line tri- states
,
address buss, thus allowing external devices
t,
'
control the buss. Consult MOS TECHNOLOGY
6502 Hardware Manual for details. (For DMA use,
the solder jumper on the board, marked
"DMA",
must be broken.
)
For the 6502 microprocessor, the RDY
line is used to halt the processor for single step-
ping, or slow ROM applications. Refer to Apple
"Tech Notes" for examples.
SOFTWARE CONSIDERATIONS:
The sequences listedbelow are the routines
used to read the keyboard or output to the display,
Read Key from KBD:
LDA KBD CR (D011)
LDA KBD DATA (DQlo)
Output to Display:
BIT DSP (D012)
STA DSP (Do12)
PIA Internal Registers:
KBD Data I3010
High order bit equals 1.
KBD Control Reg. Doll
High order bit indicates "key ready".
Reading key clears flag. Rising
edge of KBD sets flag.
DSP DATA
D012
Lower seven bits are data output,
high order bit
is
display ready"
input (1 equals ready,
0
equals busy)
DSP Control Reg. D013
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